2026-10-13T04:00:04Z https://www.scidb.cn/oai

10.57760/sciencedb.11950 2023-10-08T14:03:01Z

2023-10-08 An FPGA Based High Performance Stateful Packet Processing Method doi:10.57760/sciencedb.11950 en fig1-8.pdf were generated by microsoft visio drawing; draw1-2, draw_lut.pdf were generated by python matpltlib library. the data in draw_1-2.pdf was generated by software simulation procedure. And, data of draw_lut.pdf was generated by xilinx Vivado 2020.2.The data of table 2 was also generated by xilinx Vivado 2020.2. Table1 was the descrption of module's parameter and implement. Table 3 was the descrption of current method's performance.And we also include Xilinx Ultrascale+ and Kintex-7 FPGA experiment. FPGA; Stateful Data Plane; Configurable; Dynamic Schedule Rui Lu PUBLIC https://creativecommons.org/publicdomain/zero/1.0/ dataset Science Data Bank