2026-10-14T23:40:50Z https://www.scidb.cn/oai

10.57760/sciencedb.40888 2026-07-06T22:10:36Z

2026-07-06 Database of the 1.25-GS/s 12-Bit Inter-Stage Gain Calibration-Free Pipelined ADC with Ring Amplifiers doi:10.57760/sciencedb.40888 en This dataset contains the raw simulation results of the 1.25-GS/s 12 Bit Piped ADC circuit. Includes the following results: amplitude frequency curve, phase frequency curve, and establishment error of RingAMP with and without gain enhancement output stage; Monte Carlo simulation results of the second static current using RingAMP with and without current mirror bias technology; Transient waveforms and THD simulation results of RingAMP (the first stage inter stage amplifier of the ADC) using input splitting technology, current mirror bias technology, and gain enhancement stage under different PVTs; The frequency spectrum of the ADC designed based on RingAMP at low and high frequencies, as well as the SFDR and SNDR at different PVTs.  ADC; pipelined; RingAMP song fang ning Guo Xuan Jia Hanbo Xu Jingyuan Ren Wenhao Xu Fangyuan Liu Xinyu RESTRICTED dataset http://www.doi.org/10.1016/j.mejo.2026.107209 Science Data Bank