<?xml version="1.0" encoding="UTF-8"?>

<?xml-stylesheet type="text/xsl" href="/static/oaitohtml.xsl"?>

<!--
<?xml-stylesheet type="text/xsl" href="/oaitohtml.xsl"?>
-->

<OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
    <responseDate>2026-10-13T10:21:14Z</responseDate>
    <request verb="GetRecord" metadataPrefix="oai_dc" identifier="10.57760/sciencedb.43166" >https://www.scidb.cn/oai</request>
<GetRecord>
    <record>
    <header >
    <identifier>10.57760/sciencedb.43166</identifier>
    <datestamp>2026-07-28T14:37:33Z</datestamp>
</header>
    <metadata>
        
<oai_dc:dc xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
  <dc:date>2026-07-28</dc:date>
  <dc:title>Data for: A Stress-Recovered Bottom Dielectric Isolation Scheme for GAA Nanosheet Transistors with Self-Aligned Backside Contact Integration</dc:title>
  <dc:identifier>doi:10.57760/sciencedb.43166</dc:identifier>
  <dc:language>en</dc:language>
  <dc:description>This dataset provides the supporting data for the article &amp;ldquo;A Stress-Recovered Bottom Dielectric Isolation Scheme for GAA Nanosheet Transistors with Self-Aligned Backside Contact Integration&amp;rdquo; published in Microelectronics Journal. The dataset includes raw numerical data and original figures used for device- and circuit-level evaluation of standard GAA, Full-BDI, and SR-BDI nanosheet transistors. The numerical files include transfer characteristics, carrier mobility, RO results, SRAM performance metrics, and related comparison data obtained from TCAD and circuit-level simulations. These data support the analysis of channel stress recovery, drive-current enhancement, capacitance reduction, and RO/SRAM performance improvements enabled by the proposed SR-BDI architecture.</dc:description>
  <dc:subject>GAA nanosheet transistor; bottom dielectric isolation; SR-BDI; backside contact integration; TCAD simulation; channel stress</dc:subject>
  <dc:creator>shiqi cao</dc:creator>
  <dc:creator>liuhaoyan</dc:creator>
  <dc:creator>Yongliang Li</dc:creator>
  <dc:rights>RESTRICTED</dc:rights>
  <dc:type>dataset</dc:type>
  <dc:publisher>Science Data Bank</dc:publisher>
</oai_dc:dc>

    </metadata>
</record>
</GetRecord>
</OAI-PMH>