2026-10-13T11:36:34Z https://www.scidb.cn/oai

10.57760/sciencedb.j00173.00060 2026-05-15T10:13:42Z

2026-05-15 251059 EP丨Design of a Timing-Controlled Non-Volatile Flip-Flop with Low- Switching-Ratio FeFET doi:10.57760/sciencedb.j00173.00060 en Authors: Du Shimin*, Yang Chang, Wang Lunyao, Zhang ZheAuthor: College of Science & Technology, Ningbo UniversityCorresponding author: Du Shimin, dushimin@nbu.edu.cnOpen source date: May 14th, 2026 Fund projects: National Natural Science Foundation of China (U23A20351, 62304115); Natural Science Foundation of Zhejiang Province (LDT23F04021F04, LDT23F04021), Open Project of Ningbo Key Laboratory of Intelligent Home Appliances(20250621) Open source content Design of a Timing-Controlled Non-Volatile Flip-Flop with Low- Switching-Ratio FeFET Abstract:   Nonvolatile flip-flops (NVFFs) based on ferroelectric field-effect transistors (FeFETs) offer efficient, high-speed data backup and restoration, making them a promising approach for enhancing the performance of nonvolatile processors (NVPs). However, studies have shown that when the FeFET on/off ratio degrades, conventional single-ended flip-flops become susceptible to contention among the MOSFETs inside the latch during power-off recovery. This contention can alter the stored state of the FeFET, leading to data restoration failures. To address this issue, this paper proposes a single-ended recovery circuit tailored for the static single-phase contention-free flip-flop (SSCFF). The proposed structure keeps the FeFET write node at a high level when CLK = 0, thereby eliminating at the source the contention-induced alteration of the FeFET state. Meanwhile, a dual-phase recovery mechanism based on “precharge and state-controlled discharge” is introduced to achieve precise restoration of the pre-power-off data. Experimental results show that the proposed scheme maintains a 100% restoration rate over 2000 Monte Carlo simulations even when the FeFET on/off ratio drops to 10², which reduces the required on/off ratio by two orders of magnitude compared with existing single-ended designs. Furthermore, while sustaining femtojoule (fJ)-level restoration energy, the design reduces the worst-case hold time by 64.6% and the clock-to-output delay by 33.9%. Ferroelectric Field Effect Transistor; Nonvolatile Flip-Flop; Single-Ended Structure; Static Contention-Free Single-Phase-Clocked Flip Flop Du Shimin Yang Chang Wang Lunyao Zhang Zhe RESTRICTED dataset Science Data Bank