2026-10-12T05:11:43Z https://www.scidb.cn/oai

10.57760/sciencedb.j00273.00071 2026-07-09T17:01:47Z

2026-07-09 Research status and prospects of cryogenic storage for superconductor digital computing doi:10.57760/sciencedb.j00273.00071 en Superconducting digital circuits, with their extremely low power consumption and picosecond switching speed, are considered a key candidate for high-performance computing systems in the post-Moore's Law era. However, compared to mature superconducting logic technologies, high-performance, scalable cryogenic memory technologies remain relatively underdeveloped, becoming a critical bottleneck restricting the development of superconducting digital computing systems. This paper systematically reviews the research progress and architecture of cryogenic memory technologies. First, we analyze the core challenges faced in memory design under cryogenic conditions, including compatibility issues with superconducting logic circuits and storage density bottleneck. Subsequently, from the perspective of memory hierarchy, we focus on reviewing superconducting shift registers, cache based on superconducting matrix random-access memory, and main memory schemes based on cryo-CMOS, and compares the advantages and disadvantages of different technical approaches in terms of speed, density, power consumption, and scalability. Finally, this paper discusses the interface circuit technologies required to achieve efficient interconnection between superconducting caches and semiconductor main memory, including clock matching and signal amplification mechanisms, and looks forward to the future development direction of superconducting hierarchical memory systems. superconductor digital circuits; cryogenic memory; memory hierarchy; superconductor-CMOS interface feng li Peng Wei PUBLIC https://creativecommons.org/licenses/by-nc-sa/4.0/ dataset Science Data Bank